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[/] [xge_mac/] - Rev 26

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Rev Log message Author Age Path
26 Fix packet count antanguay 4226d 21h /xge_mac/
25 Timing improvements, reduced FIFO size from 1024 to 512 antanguay 4226d 23h /xge_mac/
24 Use FIFO's for statistics clock domain crossing antanguay 4227d 00h /xge_mac/
23 Adding basic packet stats antanguay 4227d 06h /xge_mac/
22 Added prototype system verilog testbench antanguay 4229d 03h /xge_mac/
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4229d 03h /xge_mac/
20 Updates for Xilinx synthesis antanguay 4518d 21h /xge_mac/
19 Updates for 32/64 bit systems antanguay 4693d 23h /xge_mac/
18 Updates for linux 32-bit antanguay 4694d 19h /xge_mac/
17 Fixed deprecated SystemC warnings antanguay 4697d 03h /xge_mac/
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4697d 09h /xge_mac/
15 Updated for Verilator 3.813 antanguay 4716d 10h /xge_mac/
14 Change interface to big endian, added serdes examples to testbench antanguay 5305d 04h /xge_mac/
13 Change interface to big endian, added serdes examples to testbench antanguay 5305d 05h /xge_mac/
12 Change interface to big endian, added serdes examples to testbench antanguay 5305d 05h /xge_mac/
11 Fixed clock crossing antanguay 5411d 02h /xge_mac/
10 Added details to spec antanguay 5508d 21h /xge_mac/
9 Added old uploaded documents to new repository. root 5583d 09h /xge_mac/
8 Added old uploaded documents to new repository. root 5583d 14h /xge_mac/
7 New directory structure. root 5583d 14h /xge_mac/

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