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[/] [xge_mac/] [trunk/] [rtl/] - Rev 21

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Rev Log message Author Age Path
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4229d 03h /xge_mac/trunk/rtl/
20 Updates for Xilinx synthesis antanguay 4518d 21h /xge_mac/trunk/rtl/
12 Change interface to big endian, added serdes examples to testbench antanguay 5305d 05h /xge_mac/trunk/rtl/
11 Fixed clock crossing antanguay 5411d 02h /xge_mac/trunk/rtl/
10 Added details to spec antanguay 5508d 21h /xge_mac/trunk/rtl/
7 New directory structure. root 5583d 14h /xge_mac/trunk/rtl/
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5859d 22h /trunk/rtl/
5 Fixed compilation antanguay 5865d 22h /trunk/rtl/
2 Initial revision antanguay 5866d 02h /trunk/rtl/

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