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URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] - Rev 28

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Rev Log message Author Age Path
28 Adding parameter for max frame size antanguay 4193d 00h /xge_mac/trunk/rtl/
27 Fix octets stats on barrel shift transitions antanguay 4241d 23h /xge_mac/trunk/rtl/
26 Fix packet count antanguay 4247d 23h /xge_mac/trunk/rtl/
25 Timing improvements, reduced FIFO size from 1024 to 512 antanguay 4248d 01h /xge_mac/trunk/rtl/
24 Use FIFO's for statistics clock domain crossing antanguay 4248d 02h /xge_mac/trunk/rtl/
23 Adding basic packet stats antanguay 4248d 08h /xge_mac/trunk/rtl/
22 Added prototype system verilog testbench antanguay 4250d 05h /xge_mac/trunk/rtl/
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4250d 05h /xge_mac/trunk/rtl/
20 Updates for Xilinx synthesis antanguay 4540d 00h /xge_mac/trunk/rtl/
12 Change interface to big endian, added serdes examples to testbench antanguay 5326d 07h /xge_mac/trunk/rtl/
11 Fixed clock crossing antanguay 5432d 05h /xge_mac/trunk/rtl/
10 Added details to spec antanguay 5530d 00h /xge_mac/trunk/rtl/
7 New directory structure. root 5604d 17h /xge_mac/trunk/rtl/
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5881d 00h /trunk/rtl/
5 Fixed compilation antanguay 5887d 01h /trunk/rtl/
2 Initial revision antanguay 5887d 04h /trunk/rtl/

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