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URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] - Rev 28

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Rev Log message Author Age Path
28 Adding parameter for max frame size antanguay 4181d 13h /xge_mac/trunk/rtl/
27 Fix octets stats on barrel shift transitions antanguay 4230d 13h /xge_mac/trunk/rtl/
26 Fix packet count antanguay 4236d 13h /xge_mac/trunk/rtl/
25 Timing improvements, reduced FIFO size from 1024 to 512 antanguay 4236d 15h /xge_mac/trunk/rtl/
24 Use FIFO's for statistics clock domain crossing antanguay 4236d 16h /xge_mac/trunk/rtl/
23 Adding basic packet stats antanguay 4236d 22h /xge_mac/trunk/rtl/
22 Added prototype system verilog testbench antanguay 4238d 19h /xge_mac/trunk/rtl/
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4238d 19h /xge_mac/trunk/rtl/
20 Updates for Xilinx synthesis antanguay 4528d 13h /xge_mac/trunk/rtl/
12 Change interface to big endian, added serdes examples to testbench antanguay 5314d 21h /xge_mac/trunk/rtl/
11 Fixed clock crossing antanguay 5420d 18h /xge_mac/trunk/rtl/
10 Added details to spec antanguay 5518d 13h /xge_mac/trunk/rtl/
7 New directory structure. root 5593d 06h /xge_mac/trunk/rtl/
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5869d 14h /trunk/rtl/
5 Fixed compilation antanguay 5875d 14h /trunk/rtl/
2 Initial revision antanguay 5875d 18h /trunk/rtl/

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