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[/] [xge_mac/] [trunk/] [rtl/] [include/] - Rev 24

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Rev Log message Author Age Path
24 Use FIFO's for statistics clock domain crossing antanguay 4226d 23h /xge_mac/trunk/rtl/include/
23 Adding basic packet stats antanguay 4227d 05h /xge_mac/trunk/rtl/include/
22 Added prototype system verilog testbench antanguay 4229d 02h /xge_mac/trunk/rtl/include/
12 Change interface to big endian, added serdes examples to testbench antanguay 5305d 04h /xge_mac/trunk/rtl/include/
7 New directory structure. root 5583d 13h /xge_mac/trunk/rtl/include/
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5859d 21h /xge_mac/trunk/rtl/include/
2 Initial revision antanguay 5866d 01h /xge_mac/trunk/rtl/include/

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