URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] - Rev 12

Rev	Log message	Author	Age	Path
12	Change interface to big endian, added serdes examples to testbench	antanguay	5341d 18h	/xge_mac/trunk/rtl/verilog/
11	Fixed clock crossing	antanguay	5447d 15h	/xge_mac/trunk/rtl/verilog/
10	Added details to spec	antanguay	5545d 10h	/xge_mac/trunk/rtl/verilog/
7	New directory structure.	root	5620d 03h	/xge_mac/trunk/rtl/verilog/
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5896d 11h	/xge_mac/trunk/rtl/verilog/
5	Fixed compilation	antanguay	5902d 11h	/xge_mac/trunk/rtl/verilog/
2	Initial revision	antanguay	5902d 15h	/xge_mac/trunk/rtl/verilog/