URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] - Rev 15

Rev	Log message	Author	Age	Path
12	Change interface to big endian, added serdes examples to testbench	antanguay	5321d 17h	/xge_mac/trunk/rtl/verilog/
11	Fixed clock crossing	antanguay	5427d 14h	/xge_mac/trunk/rtl/verilog/
10	Added details to spec	antanguay	5525d 09h	/xge_mac/trunk/rtl/verilog/
7	New directory structure.	root	5600d 02h	/xge_mac/trunk/rtl/verilog/
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5876d 10h	/xge_mac/trunk/rtl/verilog/
5	Fixed compilation	antanguay	5882d 10h	/xge_mac/trunk/rtl/verilog/
2	Initial revision	antanguay	5882d 13h	/xge_mac/trunk/rtl/verilog/