URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] - Rev 18

Rev	Log message	Author	Age	Path
12	Change interface to big endian, added serdes examples to testbench	antanguay	5352d 03h	/xge_mac/trunk/rtl/verilog/
11	Fixed clock crossing	antanguay	5458d 00h	/xge_mac/trunk/rtl/verilog/
10	Added details to spec	antanguay	5555d 19h	/xge_mac/trunk/rtl/verilog/
7	New directory structure.	root	5630d 12h	/xge_mac/trunk/rtl/verilog/
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5906d 20h	/xge_mac/trunk/rtl/verilog/
5	Fixed compilation	antanguay	5912d 20h	/xge_mac/trunk/rtl/verilog/
2	Initial revision	antanguay	5913d 00h	/xge_mac/trunk/rtl/verilog/