URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] - Rev 23

Rev	Log message	Author	Age	Path
23	Adding basic packet stats	antanguay	4276d 12h	/xge_mac/trunk/rtl/verilog/
22	Added prototype system verilog testbench	antanguay	4278d 08h	/xge_mac/trunk/rtl/verilog/
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4278d 08h	/xge_mac/trunk/rtl/verilog/
20	Updates for Xilinx synthesis	antanguay	4568d 03h	/xge_mac/trunk/rtl/verilog/
12	Change interface to big endian, added serdes examples to testbench	antanguay	5354d 10h	/xge_mac/trunk/rtl/verilog/
11	Fixed clock crossing	antanguay	5460d 08h	/xge_mac/trunk/rtl/verilog/
10	Added details to spec	antanguay	5558d 03h	/xge_mac/trunk/rtl/verilog/
7	New directory structure.	root	5632d 20h	/xge_mac/trunk/rtl/verilog/
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5909d 03h	/xge_mac/trunk/rtl/verilog/
5	Fixed compilation	antanguay	5915d 04h	/xge_mac/trunk/rtl/verilog/
2	Initial revision	antanguay	5915d 07h	/xge_mac/trunk/rtl/verilog/