URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] - Rev 25

Rev	Log message	Author	Age	Path
25	Timing improvements, reduced FIFO size from 1024 to 512	antanguay	4368d 02h	/xge_mac/trunk/rtl/verilog/
24	Use FIFO's for statistics clock domain crossing	antanguay	4368d 04h	/xge_mac/trunk/rtl/verilog/
23	Adding basic packet stats	antanguay	4368d 10h	/xge_mac/trunk/rtl/verilog/
22	Added prototype system verilog testbench	antanguay	4370d 07h	/xge_mac/trunk/rtl/verilog/
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4370d 07h	/xge_mac/trunk/rtl/verilog/
20	Updates for Xilinx synthesis	antanguay	4660d 01h	/xge_mac/trunk/rtl/verilog/
12	Change interface to big endian, added serdes examples to testbench	antanguay	5446d 09h	/xge_mac/trunk/rtl/verilog/
11	Fixed clock crossing	antanguay	5552d 06h	/xge_mac/trunk/rtl/verilog/
10	Added details to spec	antanguay	5650d 01h	/xge_mac/trunk/rtl/verilog/
7	New directory structure.	root	5724d 18h	/xge_mac/trunk/rtl/verilog/
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	6001d 02h	/xge_mac/trunk/rtl/verilog/
5	Fixed compilation	antanguay	6007d 02h	/xge_mac/trunk/rtl/verilog/
2	Initial revision	antanguay	6007d 06h	/xge_mac/trunk/rtl/verilog/