URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] - Rev 28

Rev	Log message	Author	Age	Path
28	Adding parameter for max frame size	antanguay	4172d 02h	/xge_mac/trunk/rtl/verilog/
27	Fix octets stats on barrel shift transitions	antanguay	4221d 01h	/xge_mac/trunk/rtl/verilog/
26	Fix packet count	antanguay	4227d 02h	/xge_mac/trunk/rtl/verilog/
25	Timing improvements, reduced FIFO size from 1024 to 512	antanguay	4227d 03h	/xge_mac/trunk/rtl/verilog/
24	Use FIFO's for statistics clock domain crossing	antanguay	4227d 05h	/xge_mac/trunk/rtl/verilog/
23	Adding basic packet stats	antanguay	4227d 11h	/xge_mac/trunk/rtl/verilog/
22	Added prototype system verilog testbench	antanguay	4229d 07h	/xge_mac/trunk/rtl/verilog/
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4229d 08h	/xge_mac/trunk/rtl/verilog/
20	Updates for Xilinx synthesis	antanguay	4519d 02h	/xge_mac/trunk/rtl/verilog/
12	Change interface to big endian, added serdes examples to testbench	antanguay	5305d 10h	/xge_mac/trunk/rtl/verilog/
11	Fixed clock crossing	antanguay	5411d 07h	/xge_mac/trunk/rtl/verilog/
10	Added details to spec	antanguay	5509d 02h	/xge_mac/trunk/rtl/verilog/
7	New directory structure.	root	5583d 19h	/xge_mac/trunk/rtl/verilog/
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5860d 03h	/xge_mac/trunk/rtl/verilog/
5	Fixed compilation	antanguay	5866d 03h	/xge_mac/trunk/rtl/verilog/
2	Initial revision	antanguay	5866d 07h	/xge_mac/trunk/rtl/verilog/