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Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [tbench/] - Rev 30

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Rev Log message Author Age Path
30 Changes to testbench to support Icarus simulator antanguay 4140d 18h /xge_mac/trunk/tbench/
29 Adding parameter for max frame size antanguay 4147d 08h /xge_mac/trunk/tbench/
25 Timing improvements, reduced FIFO size from 1024 to 512 antanguay 4202d 09h /xge_mac/trunk/tbench/
24 Use FIFO's for statistics clock domain crossing antanguay 4202d 11h /xge_mac/trunk/tbench/
23 Adding basic packet stats antanguay 4202d 16h /xge_mac/trunk/tbench/
22 Added prototype system verilog testbench antanguay 4204d 13h /xge_mac/trunk/tbench/
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4204d 13h /xge_mac/trunk/tbench/
19 Updates for 32/64 bit systems antanguay 4669d 09h /xge_mac/trunk/tbench/
18 Updates for linux 32-bit antanguay 4670d 05h /xge_mac/trunk/tbench/
17 Fixed deprecated SystemC warnings antanguay 4672d 13h /xge_mac/trunk/tbench/
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4672d 20h /xge_mac/trunk/tbench/
15 Updated for Verilator 3.813 antanguay 4691d 20h /xge_mac/trunk/tbench/
14 Change interface to big endian, added serdes examples to testbench antanguay 5280d 14h /xge_mac/trunk/tbench/
12 Change interface to big endian, added serdes examples to testbench antanguay 5280d 15h /xge_mac/trunk/tbench/
11 Fixed clock crossing antanguay 5386d 13h /xge_mac/trunk/tbench/
7 New directory structure. root 5559d 01h /xge_mac/trunk/tbench/
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5835d 08h /trunk/tbench/
4 Created antanguay 5841d 11h /trunk/tbench/
2 Initial revision antanguay 5841d 12h /trunk/tbench/

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