URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [tbench/] - Rev 23

Rev	Log message	Author	Age	Path
23	Adding basic packet stats	antanguay	4333d 04h	/xge_mac/trunk/tbench/
22	Added prototype system verilog testbench	antanguay	4335d 01h	/xge_mac/trunk/tbench/
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4335d 01h	/xge_mac/trunk/tbench/
19	Updates for 32/64 bit systems	antanguay	4799d 20h	/xge_mac/trunk/tbench/
18	Updates for linux 32-bit	antanguay	4800d 17h	/xge_mac/trunk/tbench/
17	Fixed deprecated SystemC warnings	antanguay	4803d 01h	/xge_mac/trunk/tbench/
16	Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim	antanguay	4803d 07h	/xge_mac/trunk/tbench/
15	Updated for Verilator 3.813	antanguay	4822d 08h	/xge_mac/trunk/tbench/
14	Change interface to big endian, added serdes examples to testbench	antanguay	5411d 02h	/xge_mac/trunk/tbench/
12	Change interface to big endian, added serdes examples to testbench	antanguay	5411d 03h	/xge_mac/trunk/tbench/
11	Fixed clock crossing	antanguay	5517d 00h	/xge_mac/trunk/tbench/
7	New directory structure.	root	5689d 12h	/xge_mac/trunk/tbench/
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5965d 20h	/trunk/tbench/
4	Created	antanguay	5971d 23h	/trunk/tbench/
2	Initial revision	antanguay	5972d 00h	/trunk/tbench/