URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [tbench/] - Rev 24

Rev	Log message	Author	Age	Path
24	Use FIFO's for statistics clock domain crossing	antanguay	4239d 20h	/xge_mac/trunk/tbench/
23	Adding basic packet stats	antanguay	4240d 02h	/xge_mac/trunk/tbench/
22	Added prototype system verilog testbench	antanguay	4241d 23h	/xge_mac/trunk/tbench/
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4241d 23h	/xge_mac/trunk/tbench/
19	Updates for 32/64 bit systems	antanguay	4706d 18h	/xge_mac/trunk/tbench/
18	Updates for linux 32-bit	antanguay	4707d 15h	/xge_mac/trunk/tbench/
17	Fixed deprecated SystemC warnings	antanguay	4709d 23h	/xge_mac/trunk/tbench/
16	Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim	antanguay	4710d 05h	/xge_mac/trunk/tbench/
15	Updated for Verilator 3.813	antanguay	4729d 06h	/xge_mac/trunk/tbench/
14	Change interface to big endian, added serdes examples to testbench	antanguay	5318d 00h	/xge_mac/trunk/tbench/
12	Change interface to big endian, added serdes examples to testbench	antanguay	5318d 01h	/xge_mac/trunk/tbench/
11	Fixed clock crossing	antanguay	5423d 22h	/xge_mac/trunk/tbench/
7	New directory structure.	root	5596d 10h	/xge_mac/trunk/tbench/
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5872d 18h	/trunk/tbench/
4	Created	antanguay	5878d 21h	/trunk/tbench/
2	Initial revision	antanguay	5878d 22h	/trunk/tbench/