URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [tbench/] - Rev 28

Rev	Log message	Author	Age	Path
25	Timing improvements, reduced FIFO size from 1024 to 512	antanguay	4227d 02h	/xge_mac/trunk/tbench/
24	Use FIFO's for statistics clock domain crossing	antanguay	4227d 04h	/xge_mac/trunk/tbench/
23	Adding basic packet stats	antanguay	4227d 09h	/xge_mac/trunk/tbench/
22	Added prototype system verilog testbench	antanguay	4229d 06h	/xge_mac/trunk/tbench/
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4229d 06h	/xge_mac/trunk/tbench/
19	Updates for 32/64 bit systems	antanguay	4694d 02h	/xge_mac/trunk/tbench/
18	Updates for linux 32-bit	antanguay	4694d 22h	/xge_mac/trunk/tbench/
17	Fixed deprecated SystemC warnings	antanguay	4697d 06h	/xge_mac/trunk/tbench/
16	Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim	antanguay	4697d 13h	/xge_mac/trunk/tbench/
15	Updated for Verilator 3.813	antanguay	4716d 13h	/xge_mac/trunk/tbench/
14	Change interface to big endian, added serdes examples to testbench	antanguay	5305d 08h	/xge_mac/trunk/tbench/
12	Change interface to big endian, added serdes examples to testbench	antanguay	5305d 08h	/xge_mac/trunk/tbench/
11	Fixed clock crossing	antanguay	5411d 06h	/xge_mac/trunk/tbench/
7	New directory structure.	root	5583d 18h	/xge_mac/trunk/tbench/
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5860d 01h	/trunk/tbench/
4	Created	antanguay	5866d 04h	/trunk/tbench/
2	Initial revision	antanguay	5866d 05h	/trunk/tbench/