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[/] [xge_mac/] [trunk/] [tbench/] - Rev 31

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Rev Log message Author Age Path
30 Changes to testbench to support Icarus simulator antanguay 4158d 01h /xge_mac/trunk/tbench/
29 Adding parameter for max frame size antanguay 4164d 15h /xge_mac/trunk/tbench/
25 Timing improvements, reduced FIFO size from 1024 to 512 antanguay 4219d 17h /xge_mac/trunk/tbench/
24 Use FIFO's for statistics clock domain crossing antanguay 4219d 18h /xge_mac/trunk/tbench/
23 Adding basic packet stats antanguay 4220d 00h /xge_mac/trunk/tbench/
22 Added prototype system verilog testbench antanguay 4221d 21h /xge_mac/trunk/tbench/
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4221d 21h /xge_mac/trunk/tbench/
19 Updates for 32/64 bit systems antanguay 4686d 17h /xge_mac/trunk/tbench/
18 Updates for linux 32-bit antanguay 4687d 13h /xge_mac/trunk/tbench/
17 Fixed deprecated SystemC warnings antanguay 4689d 21h /xge_mac/trunk/tbench/
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4690d 03h /xge_mac/trunk/tbench/
15 Updated for Verilator 3.813 antanguay 4709d 04h /xge_mac/trunk/tbench/
14 Change interface to big endian, added serdes examples to testbench antanguay 5297d 22h /xge_mac/trunk/tbench/
12 Change interface to big endian, added serdes examples to testbench antanguay 5297d 23h /xge_mac/trunk/tbench/
11 Fixed clock crossing antanguay 5403d 20h /xge_mac/trunk/tbench/
7 New directory structure. root 5576d 08h /xge_mac/trunk/tbench/
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5852d 16h /trunk/tbench/
4 Created antanguay 5858d 19h /trunk/tbench/
2 Initial revision antanguay 5858d 20h /trunk/tbench/

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