URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [tbench/] [verilog/] - Rev 16

Rev	Log message	Author	Age	Path
16	Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim	antanguay	4703d 00h	/xge_mac/trunk/tbench/verilog/
14	Change interface to big endian, added serdes examples to testbench	antanguay	5310d 19h	/xge_mac/trunk/tbench/verilog/
12	Change interface to big endian, added serdes examples to testbench	antanguay	5310d 19h	/xge_mac/trunk/tbench/verilog/
11	Fixed clock crossing	antanguay	5416d 17h	/xge_mac/trunk/tbench/verilog/
7	New directory structure.	root	5589d 05h	/xge_mac/trunk/tbench/verilog/
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5865d 12h	/xge_mac/trunk/tbench/verilog/
2	Initial revision	antanguay	5871d 16h	/xge_mac/trunk/tbench/verilog/