URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [tbench/] [verilog/] - Rev 25

Rev	Log message	Author	Age	Path
24	Use FIFO's for statistics clock domain crossing	antanguay	4239d 03h	/xge_mac/trunk/tbench/verilog/
23	Adding basic packet stats	antanguay	4239d 09h	/xge_mac/trunk/tbench/verilog/
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4241d 06h	/xge_mac/trunk/tbench/verilog/
17	Fixed deprecated SystemC warnings	antanguay	4709d 06h	/xge_mac/trunk/tbench/verilog/
16	Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim	antanguay	4709d 12h	/xge_mac/trunk/tbench/verilog/
14	Change interface to big endian, added serdes examples to testbench	antanguay	5317d 07h	/xge_mac/trunk/tbench/verilog/
12	Change interface to big endian, added serdes examples to testbench	antanguay	5317d 08h	/xge_mac/trunk/tbench/verilog/
11	Fixed clock crossing	antanguay	5423d 05h	/xge_mac/trunk/tbench/verilog/
7	New directory structure.	root	5595d 17h	/xge_mac/trunk/tbench/verilog/
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5872d 01h	/xge_mac/trunk/tbench/verilog/
2	Initial revision	antanguay	5878d 05h	/xge_mac/trunk/tbench/verilog/