OpenCores
URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] - Rev 34

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
34 Added makefile for this system.
Added board simulator file for this system.
Removed simple errors from main system.		 lcdsgmtr 3050d 17h /xucpu/
33 Removal of simple compilation errors. lcdsgmtr 3050d 17h /xucpu/
32 Added necessary red tape for implementing all these components. lcdsgmtr 3050d 17h /xucpu/
31 Definition of system architecture library.
Definition of top level system architecture.
Main components used in top level system definition.		 lcdsgmtr 3050d 17h /xucpu/
30 First implementation of cache memory. lcdsgmtr 3050d 17h /xucpu/
29 All kinds of changes in different configurations. lcdsgmtr 3050d 17h /xucpu/
28 Added project files for different systems. lcdsgmtr 3202d 18h /xucpu/
27 When loading the 32k memory, do not let the process stop by a file that is
shorter, also make sure that the process is stopped if the file should be
longer.		 lcdsgmtr 3202d 18h /xucpu/
26 Added test data for 32k memory.
Added GTKW configuration file.		 lcdsgmtr 3204d 17h /xucpu/
25 Problem with memory: created conditional generate based upon data width
instead of address width.		 lcdsgmtr 3204d 17h /xucpu/
24 Starting tracing through the component hierarchy initialisation. lcdsgmtr 3204d 17h /xucpu/
23 Currently moved test bench to 10 bit address.
Created spreadsheet for filling memory with random data.
When testing, memory is apparently not initialised.		 lcdsgmtr 3204d 17h /xucpu/
22 Update on makefile, because some parts are in other files. lcdsgmtr 3204d 17h /xucpu/
21 Since all BRAM is unified in one component, this testbench is not necessary
anymore.		 lcdsgmtr 3204d 17h /xucpu/
20 Update RAM package to allow for 15-bit address.
Update test bench to use address width parameter.		 lcdsgmtr 3204d 17h /xucpu/
19 Makefile for building memory block testbench. lcdsgmtr 3204d 17h /xucpu/
18 Ignore work files from GHDL. lcdsgmtr 3204d 17h /xucpu/
17 Moving the generic block ram component piece by piece to a better
implementation.		 lcdsgmtr 3204d 17h /xucpu/
16 Re-write of memory in function of initial array memory blocks. lcdsgmtr 3204d 17h /xucpu/
15 Unification of all RAM parts into one interface. lcdsgmtr 3204d 17h /xucpu/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.