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[/] [xucpu/] [trunk/] [src/] - Rev 35

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Rev Log message Author Age Path
34 Added makefile for this system.
Added board simulator file for this system.
Removed simple errors from main system.		 lcdsgmtr 3071d 14h /xucpu/trunk/src/
33 Removal of simple compilation errors. lcdsgmtr 3071d 14h /xucpu/trunk/src/
32 Added necessary red tape for implementing all these components. lcdsgmtr 3071d 14h /xucpu/trunk/src/
31 Definition of system architecture library.
Definition of top level system architecture.
Main components used in top level system definition.		 lcdsgmtr 3071d 14h /xucpu/trunk/src/
30 First implementation of cache memory. lcdsgmtr 3071d 14h /xucpu/trunk/src/
29 All kinds of changes in different configurations. lcdsgmtr 3071d 14h /xucpu/trunk/src/
28 Added project files for different systems. lcdsgmtr 3223d 16h /xucpu/trunk/src/
27 When loading the 32k memory, do not let the process stop by a file that is
shorter, also make sure that the process is stopped if the file should be
longer.		 lcdsgmtr 3223d 16h /xucpu/trunk/src/
26 Added test data for 32k memory.
Added GTKW configuration file.		 lcdsgmtr 3225d 14h /xucpu/trunk/src/
25 Problem with memory: created conditional generate based upon data width
instead of address width.		 lcdsgmtr 3225d 14h /xucpu/trunk/src/
24 Starting tracing through the component hierarchy initialisation. lcdsgmtr 3225d 14h /xucpu/trunk/src/
23 Currently moved test bench to 10 bit address.
Created spreadsheet for filling memory with random data.
When testing, memory is apparently not initialised.		 lcdsgmtr 3225d 14h /xucpu/trunk/src/
22 Update on makefile, because some parts are in other files. lcdsgmtr 3225d 14h /xucpu/trunk/src/
21 Since all BRAM is unified in one component, this testbench is not necessary
anymore.		 lcdsgmtr 3225d 14h /xucpu/trunk/src/
20 Update RAM package to allow for 15-bit address.
Update test bench to use address width parameter.		 lcdsgmtr 3225d 14h /xucpu/trunk/src/
19 Makefile for building memory block testbench. lcdsgmtr 3225d 14h /xucpu/trunk/src/
17 Moving the generic block ram component piece by piece to a better
implementation.		 lcdsgmtr 3225d 14h /xucpu/trunk/src/
16 Re-write of memory in function of initial array memory blocks. lcdsgmtr 3225d 14h /xucpu/trunk/src/
15 Unification of all RAM parts into one interface. lcdsgmtr 3225d 14h /xucpu/trunk/src/
10 Correct build with GHDL. lcdsgmtr 3357d 15h /xucpu/trunk/src/

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