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[/] [xucpu/] [trunk/] [src/] [components/] - Rev 34

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Rev Log message Author Age Path
30 First implementation of cache memory. lcdsgmtr 3080d 15h /xucpu/trunk/src/components/
28 Added project files for different systems. lcdsgmtr 3232d 16h /xucpu/trunk/src/components/
26 Added test data for 32k memory.
Added GTKW configuration file.		 lcdsgmtr 3234d 15h /xucpu/trunk/src/components/
25 Problem with memory: created conditional generate based upon data width
instead of address width.		 lcdsgmtr 3234d 15h /xucpu/trunk/src/components/
23 Currently moved test bench to 10 bit address.
Created spreadsheet for filling memory with random data.
When testing, memory is apparently not initialised.		 lcdsgmtr 3234d 15h /xucpu/trunk/src/components/
22 Update on makefile, because some parts are in other files. lcdsgmtr 3234d 15h /xucpu/trunk/src/components/
21 Since all BRAM is unified in one component, this testbench is not necessary
anymore.		 lcdsgmtr 3234d 15h /xucpu/trunk/src/components/
20 Update RAM package to allow for 15-bit address.
Update test bench to use address width parameter.		 lcdsgmtr 3234d 15h /xucpu/trunk/src/components/
19 Makefile for building memory block testbench. lcdsgmtr 3234d 15h /xucpu/trunk/src/components/
17 Moving the generic block ram component piece by piece to a better
implementation.		 lcdsgmtr 3234d 15h /xucpu/trunk/src/components/
16 Re-write of memory in function of initial array memory blocks. lcdsgmtr 3234d 15h /xucpu/trunk/src/components/
15 Unification of all RAM parts into one interface. lcdsgmtr 3234d 15h /xucpu/trunk/src/components/
9 This makes sure that this GHDL configuration analyses correctly. lcdsgmtr 3366d 15h /xucpu/trunk/src/components/
8 Rebuilding the configuration to build the first system using GHDL. lcdsgmtr 3367d 14h /xucpu/trunk/src/components/
6 Removed some unnecessary files and directories.
Moved other files to new directories.		 lcdsgmtr 3367d 14h /xucpu/trunk/src/components/
5 Re-organisation of repository. lcdsgmtr 3368d 15h /xucpu/trunk/src/components/

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