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[/] [xucpu/] [trunk/] [src/] [components/] [BRAM/] - Rev 26

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Rev Log message Author Age Path
26 Added test data for 32k memory.
Added GTKW configuration file.		 lcdsgmtr 3226d 07h /xucpu/trunk/src/components/BRAM/
25 Problem with memory: created conditional generate based upon data width
instead of address width.		 lcdsgmtr 3226d 07h /xucpu/trunk/src/components/BRAM/
23 Currently moved test bench to 10 bit address.
Created spreadsheet for filling memory with random data.
When testing, memory is apparently not initialised.		 lcdsgmtr 3226d 07h /xucpu/trunk/src/components/BRAM/
22 Update on makefile, because some parts are in other files. lcdsgmtr 3226d 07h /xucpu/trunk/src/components/BRAM/
21 Since all BRAM is unified in one component, this testbench is not necessary
anymore.		 lcdsgmtr 3226d 07h /xucpu/trunk/src/components/BRAM/
20 Update RAM package to allow for 15-bit address.
Update test bench to use address width parameter.		 lcdsgmtr 3226d 07h /xucpu/trunk/src/components/BRAM/
19 Makefile for building memory block testbench. lcdsgmtr 3226d 07h /xucpu/trunk/src/components/BRAM/
17 Moving the generic block ram component piece by piece to a better
implementation.		 lcdsgmtr 3226d 07h /xucpu/trunk/src/components/BRAM/
16 Re-write of memory in function of initial array memory blocks. lcdsgmtr 3226d 07h /xucpu/trunk/src/components/BRAM/
15 Unification of all RAM parts into one interface. lcdsgmtr 3226d 07h /xucpu/trunk/src/components/BRAM/
5 Re-organisation of repository. lcdsgmtr 3360d 07h /xucpu/trunk/src/components/BRAM/
2 First checkin to make sure that the project does not get stale. lcdsgmtr 3482d 08h /BRAM/

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