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[/] [xulalx25soc/] - Rev 18

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Rev Log message Author Age Path
18 Got the bitfile back up to speed at 80 MHz. dgisselq 3121d 13h /xulalx25soc/
17 Some basic updates, to include adding in a missing file (zipstate). Most of
these updates include making sure that the XuLA2 device can be accessed via
the USB. (Prior versions accessed the FPGA via serial port or network ...)		 dgisselq 3121d 13h /xulalx25soc/
16 Updates to allow a test of the ICAP configuration interface. dgisselq 3121d 13h /xulalx25soc/
15 WORKING VERSION! ... or, at least the memory test works. dgisselq 3123d 09h /xulalx25soc/
14 Quick bug fix. dgisselq 3123d 09h /xulalx25soc/
13 This version is now working. (It probably would've worked before, but
everything is now working.)		 dgisselq 3123d 09h /xulalx25soc/
12 Modified to match the settings I'm now using within ISE. dgisselq 3123d 12h /xulalx25soc/
11 Getting software up and running on the board for the first time. (Not there
yet, but I think these items have now proven themselves.)		 dgisselq 3123d 12h /xulalx25soc/
10 Changed the name of the memtest.s file. dgisselq 3123d 12h /xulalx25soc/
9 Bug fixes, optimizations, etc. as part of building for an actual hardware
implementation. Most notably, the speed was lowered from 80MHz down to
76 MHz.		 dgisselq 3123d 12h /xulalx25soc/
8 Added an interface description to the comments at the top of the file. dgisselq 3125d 21h /xulalx25soc/
7 Mostly minor changes. Fixed the legal copyright statement in the UART files,
adjusted some comments, and made sure that the zipdbg program contained all
the latest features from our Vault.		 dgisselq 3125d 22h /xulalx25soc/
6 Initial file load, likely to be buggy, but the initial load nonetheless. dgisselq 3126d 08h /xulalx25soc/
5 Initial software version, in support of the project. At this point, they are
provided with no guarantees that they work. (They did use to work--on an older
build, but I haven't been able to verify that they work with this newer build
yet.)		 dgisselq 3126d 08h /xulalx25soc/
4 Here's an initial, albeit incomplete, build. dgisselq 3126d 08h /xulalx25soc/
3 dgisselq 3126d 08h /xulalx25soc/
2 A very first, albeit incomplete, build. dgisselq 3126d 08h /xulalx25soc/
1 The project and the structure was created root 3126d 10h /xulalx25soc/

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