OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] - Rev 21

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
21 Files, not links, to replace what were once broken links in this project. dgisselq 3073d 14h /xulalx25soc/
20 Documents, borrowed from their source projects, and reproduced here. These
describe the various components of the board.		 dgisselq 3073d 14h /xulalx25soc/
19 Step one in fixing soft link poblems. The following files were soft links,
and not brought into the svn repository properly. They'll be replaced in the
next update with their full sources.		 dgisselq 3073d 14h /xulalx25soc/
18 Got the bitfile back up to speed at 80 MHz. dgisselq 3077d 05h /xulalx25soc/
17 Some basic updates, to include adding in a missing file (zipstate). Most of
these updates include making sure that the XuLA2 device can be accessed via
the USB. (Prior versions accessed the FPGA via serial port or network ...)		 dgisselq 3077d 05h /xulalx25soc/
16 Updates to allow a test of the ICAP configuration interface. dgisselq 3077d 05h /xulalx25soc/
15 WORKING VERSION! ... or, at least the memory test works. dgisselq 3079d 00h /xulalx25soc/
14 Quick bug fix. dgisselq 3079d 00h /xulalx25soc/
13 This version is now working. (It probably would've worked before, but
everything is now working.)		 dgisselq 3079d 00h /xulalx25soc/
12 Modified to match the settings I'm now using within ISE. dgisselq 3079d 03h /xulalx25soc/
11 Getting software up and running on the board for the first time. (Not there
yet, but I think these items have now proven themselves.)		 dgisselq 3079d 03h /xulalx25soc/
10 Changed the name of the memtest.s file. dgisselq 3079d 03h /xulalx25soc/
9 Bug fixes, optimizations, etc. as part of building for an actual hardware
implementation. Most notably, the speed was lowered from 80MHz down to
76 MHz.		 dgisselq 3079d 03h /xulalx25soc/
8 Added an interface description to the comments at the top of the file. dgisselq 3081d 13h /xulalx25soc/
7 Mostly minor changes. Fixed the legal copyright statement in the UART files,
adjusted some comments, and made sure that the zipdbg program contained all
the latest features from our Vault.		 dgisselq 3081d 13h /xulalx25soc/
6 Initial file load, likely to be buggy, but the initial load nonetheless. dgisselq 3081d 23h /xulalx25soc/
5 Initial software version, in support of the project. At this point, they are
provided with no guarantees that they work. (They did use to work--on an older
build, but I haven't been able to verify that they work with this newer build
yet.)		 dgisselq 3081d 23h /xulalx25soc/
4 Here's an initial, albeit incomplete, build. dgisselq 3082d 00h /xulalx25soc/
3 dgisselq 3082d 00h /xulalx25soc/
2 A very first, albeit incomplete, build. dgisselq 3082d 00h /xulalx25soc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.