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[/] [xulalx25soc/] - Rev 88

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88 Adjusted copyright date. dgisselq 2910d 19h /xulalx25soc/
87 Placed the interrupt into the carry chain for less logic area. dgisselq 2910d 19h /xulalx25soc/
86 Fine tuning the `defines, so that you can build pipelined without pipelined
bus access and so forth.		 dgisselq 2910d 19h /xulalx25soc/
85 First version of the SD-SPI interface, with partial functionality. (No the
empty link that was here before.)		 dgisselq 2914d 16h /xulalx25soc/
84 First part of switching to proper sdspi.v, and not just the link. dgisselq 2914d 16h /xulalx25soc/
83 Fixes a bug in the LX9 build whereby the flash was never ever granted permission
to use the SPI port.		 dgisselq 2915d 20h /xulalx25soc/
82 dgisselq 2916d 15h /xulalx25soc/
81 Adds register values for the SD-Card registers. dgisselq 2916d 15h /xulalx25soc/
80 Currently working version: contains both a working DMA controller as well as
a working (as far as I can tell) SD-Card controller (writes not yet tested).		 dgisselq 2916d 15h /xulalx25soc/
79 Adds 'bench' and 'sw' targets, and automatically builds them (now). dgisselq 2916d 15h /xulalx25soc/
78 Comments out the line that caused a compiler warning--setting an unused
variable. Code should be better as a result.		 dgisselq 2916d 15h /xulalx25soc/
77 Adds register names and values for the SD card interface. dgisselq 2916d 15h /xulalx25soc/
76 Now tries to avoid reading from the stack if the stack addresses are already
known to be bad. That way, the debugger tries to preserve any bus error address
already on the buserr device.		 dgisselq 2916d 15h /xulalx25soc/
75 Added simulation capability for the SD-Card, as well as debugging output for the
DMA. (The SD-Card debug may not be fully featured, yet, but it has gotten me
to where I can talk to the card.)		 dgisselq 2916d 15h /xulalx25soc/
74 Adds the SD-card capability, and connects the debug wires to/from the uartdev
in case it needs to be debugged.		 dgisselq 2916d 15h /xulalx25soc/
73 Simplified logic. dgisselq 2916d 15h /xulalx25soc/
72 Sets XULA25 as the default. dgisselq 2916d 16h /xulalx25soc/
71 Needed to play with subtle timing to get this to build. Expect me to play
with these two clock numbers more.		 dgisselq 2916d 16h /xulalx25soc/
70 Cosmetic (minor) update. dgisselq 2916d 16h /xulalx25soc/
69 Massive logic simplification. This is also the first (verified) working
version.		 dgisselq 2916d 16h /xulalx25soc/

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