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[/] [xulalx25soc/] [trunk/] - Rev 41

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41 Bug fix. This was preventing dumpsdram from accurately reading back what
had been written to the RAM earlier.
dgisselq 2996d 09h /xulalx25soc/trunk/
40 This adds to dumpsdram the capability to run over a port, such as with
busmaster_tb.
dgisselq 2997d 20h /xulalx25soc/trunk/
39 An attempt at a bugfix. We'll see if this works any better downstream. dgisselq 2999d 16h /xulalx25soc/trunk/
38 Updated to remove the build dependence upon ZipCPU. dgisselq 2999d 19h /xulalx25soc/trunk/
37 These fixes were necessary to get the SDRAM into a working simulation
capability. It is finally what it was supposed to be: cycle accurate. Sadly,
to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
a problem with external input clocking in Verilator. This fixes it--but its
a Verilator only change--to rtl/wbsdram.v that is.)
dgisselq 3000d 13h /xulalx25soc/trunk/
36 A linker script, appropriate to the XuLA25-LX25 SoC. dgisselq 3000d 15h /xulalx25soc/trunk/
35 Updates the memory testing program to work successfully with the Gnu build
tools--particularly the GNU C-preprocessor from GCC and the GNU assembler from
Binutils.
dgisselq 3000d 15h /xulalx25soc/trunk/
34 Bug fix: This sets as a positive voltage bias (not negative) the maximum
value of 0x07fff, where as the negative maximum value of 0x08000 properly
(now) reflects nearly ground--as one would desire. (Last time around I had
these backwards.)
dgisselq 3004d 10h /xulalx25soc/trunk/
33 Oops -- the audio was wired audio first then the interrupt controller, not
the other way around. This adjusts regdefs to match what's on the chip.
dgisselq 3004d 12h /xulalx25soc/trunk/
32 Just noticed that the timer was fixed on this. This change adjusts the
timer to support audio at a user selectable rate.
dgisselq 3004d 12h /xulalx25soc/trunk/
31 A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25.
dgisselq 3004d 12h /xulalx25soc/trunk/
30 Bug fixes. In particular, this fixes a segmentation violation. dgisselq 3004d 16h /xulalx25soc/trunk/
29 This adds a vastly updated and superious ziprun capability to the repository.
ziprun now accepts ELF program files *only*, reads them, and places them onto
the board. This includes the ability, within the ELF file, of specifying
whether or not the data is sent to block ram, SD ram, or Flash, as well as
the ability of specifying the initial address. (Of course, that's a one time
thing--to always have the same initial address, set the address in
rtl/busmaster.v)
dgisselq 3005d 08h /xulalx25soc/trunk/
28 Oops--two files needed by zipdbg weren't originally placed in the directory. dgisselq 3005d 13h /xulalx25soc/trunk/
27 Bug fix: the last_state register now correctly reflects all 5-bits of the state
machine. (Useful when detecting lockups ...)
dgisselq 3005d 13h /xulalx25soc/trunk/
26 Some bug fixes, and the long jump early branching integration. dgisselq 3005d 13h /xulalx25soc/trunk/
25 Fixing compile time warnings. dgisselq 3005d 13h /xulalx25soc/trunk/
24 Added the #define necessary to enable (and clear) SCOPE interrupts. dgisselq 3011d 11h /xulalx25soc/trunk/
23 This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update.
dgisselq 3013d 23h /xulalx25soc/trunk/
22 Added the mkdatev.pl file. (Oops!) dgisselq 3016d 15h /xulalx25soc/trunk/

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