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[/] [xulalx25soc/] [trunk/] - Rev 67

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Rev Log message Author Age Path
67 Simplifies logic, and guarantees that the minimum set value will always
produce an int. For example, if the count was X before, setting X-1 wouldn't
produce an interrupt since it had passed. Now it produces an interrupt, and
keeps the next interrupt valid.		 dgisselq 2914d 07h /xulalx25soc/trunk/
66 Simplified logic (barely). dgisselq 2914d 08h /xulalx25soc/trunk/
65 Makes the auto-reload feature a parameterized (generic) feature, so the same
code will work for both auto-reloadable and non-autoreloadable (i.e. watchdog)
timers.		 dgisselq 2914d 08h /xulalx25soc/trunk/
64 First (verified) working version. dgisselq 2914d 08h /xulalx25soc/trunk/
63 Simplified logic. dgisselq 2914d 08h /xulalx25soc/trunk/
62 Removed the pipe logic from the non-pipelined version, and made the NOOP a
specific ALU instruction so that the PC is always properly updated.		 dgisselq 2914d 08h /xulalx25soc/trunk/
61 Fixed the timing control wires: busy and valid will never both be true. Busy
will be true (now) until valid is asserted, and busy will never not be
asserted until valid is true.		 dgisselq 2914d 08h /xulalx25soc/trunk/
60 LONG_MPY upgrade. This is part of swapping out the LDIHI instruction for a
MPY, and the MPYS and MPYU instructions for MPYSHI and MPYUHI respectively.		 dgisselq 2914d 08h /xulalx25soc/trunk/
59 Simplified logic. dgisselq 2914d 08h /xulalx25soc/trunk/
58 Bug fix: the UART can now be reconfigured post-boot without a BREAK condition. dgisselq 2914d 08h /xulalx25soc/trunk/
57 Fixed the TX/RX addresses so that they match the documentation: TX first, then
RX.		 dgisselq 2922d 07h /xulalx25soc/trunk/
56 Brings code in line with the OpenCores core: parameterizes the reload value,
and the number of bits in the timer.		 dgisselq 2922d 07h /xulalx25soc/trunk/
55 Updated copyright notice. dgisselq 2922d 08h /xulalx25soc/trunk/
54 Updated copyright notice. dgisselq 2922d 08h /xulalx25soc/trunk/
53 Added a touch of error checking. dgisselq 2962d 08h /xulalx25soc/trunk/
52 This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change.		 dgisselq 2962d 08h /xulalx25soc/trunk/
51 Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags.		 dgisselq 2972d 06h /xulalx25soc/trunk/
50 Updates to fix some broken early branching code, both in idecode and pfcache. dgisselq 2981d 09h /xulalx25soc/trunk/
49 Added some documentation to make the read and write calls easier to understand. dgisselq 2990d 09h /xulalx25soc/trunk/
48 Cleaned up the documentation a touch. It no longer reads like the bugs I used
to debug are still being debugged ...		 dgisselq 2992d 11h /xulalx25soc/trunk/

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