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[/] [xulalx25soc/] [trunk/] [bench/] - Rev 70

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47 Fixes the "NAN" clocks/second output, as well as making input timing come closer
to a realistic timing. (I actually don't know what timing the JTAG port is
providing, but ... the new timer is closer.)		 dgisselq 3153d 19h /xulalx25soc/trunk/bench/
37 These fixes were necessary to get the SDRAM into a working simulation
capability. It is finally what it was supposed to be: cycle accurate. Sadly,
to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
a problem with external input clocking in Verilator. This fixes it--but its
a Verilator only change--to rtl/wbsdram.v that is.)		 dgisselq 3161d 19h /xulalx25soc/trunk/bench/
36 A linker script, appropriate to the XuLA25-LX25 SoC. dgisselq 3161d 20h /xulalx25soc/trunk/bench/
35 Updates the memory testing program to work successfully with the Gnu build
tools--particularly the GNU C-preprocessor from GCC and the GNU assembler from
Binutils.		 dgisselq 3161d 21h /xulalx25soc/trunk/bench/
31 A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25.		 dgisselq 3165d 18h /xulalx25soc/trunk/bench/
16 Updates to allow a test of the ICAP configuration interface. dgisselq 3231d 18h /xulalx25soc/trunk/bench/
15 WORKING VERSION! ... or, at least the memory test works. dgisselq 3233d 14h /xulalx25soc/trunk/bench/
10 Changed the name of the memtest.s file. dgisselq 3233d 17h /xulalx25soc/trunk/bench/
4 Here's an initial, albeit incomplete, build. dgisselq 3236d 13h /xulalx25soc/trunk/bench/

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