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Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] - Rev 100

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Rev	Log message	Author	Age	Path
100	Includes updates so this can run at higher clocks speeds within an FPGA.	dgisselq	2888d 17h	/xulalx25soc/trunk/rtl/
99	Includes high-speed updates. rxuart and txuart will now run at 200MHz on an Artix-7, so should not impact timing (any more) on the XuLA platform.	dgisselq	2888d 17h	/xulalx25soc/trunk/rtl/
98	Updated copyright notices for the new year, to reflect that changes have been made in 2016.	dgisselq	2888d 17h	/xulalx25soc/trunk/rtl/
90	Reads and writes to the SD over SPI port now work. The card appears, as of now, to be fully functional.	dgisselq	2911d 21h	/xulalx25soc/trunk/rtl/
89	Bug fixes, following the adf_ce logic combining ALU/DIVIDE/FPU pipeline logic into one register, this fixes that logic so that instructions without their condition fulfilled are still "executed" and marked as done.	dgisselq	2911d 21h	/xulalx25soc/trunk/rtl/
88	Adjusted copyright date.	dgisselq	2911d 21h	/xulalx25soc/trunk/rtl/
87	Placed the interrupt into the carry chain for less logic area.	dgisselq	2911d 21h	/xulalx25soc/trunk/rtl/
86	Fine tuning the `defines, so that you can build pipelined without pipelined bus access and so forth.	dgisselq	2911d 21h	/xulalx25soc/trunk/rtl/
85	First version of the SD-SPI interface, with partial functionality. (No the empty link that was here before.)	dgisselq	2915d 18h	/xulalx25soc/trunk/rtl/
84	First part of switching to proper sdspi.v, and not just the link.	dgisselq	2915d 18h	/xulalx25soc/trunk/rtl/
83	Fixes a bug in the LX9 build whereby the flash was never ever granted permission to use the SPI port.	dgisselq	2916d 22h	/xulalx25soc/trunk/rtl/
74	Adds the SD-card capability, and connects the debug wires to/from the uartdev in case it needs to be debugged.	dgisselq	2917d 17h	/xulalx25soc/trunk/rtl/
73	Simplified logic.	dgisselq	2917d 17h	/xulalx25soc/trunk/rtl/
72	Sets XULA25 as the default.	dgisselq	2917d 18h	/xulalx25soc/trunk/rtl/
71	Needed to play with subtle timing to get this to build. Expect me to play with these two clock numbers more.	dgisselq	2917d 18h	/xulalx25soc/trunk/rtl/
70	Cosmetic (minor) update.	dgisselq	2917d 18h	/xulalx25soc/trunk/rtl/
69	Massive logic simplification. This is also the first (verified) working version.	dgisselq	2917d 18h	/xulalx25soc/trunk/rtl/
68	Fixes the debug ack line, so it no longer acks when there isn't a dbg_stb. Fixed the multiply option parameter, so it sets a 3-clock multiply properly. Adjusted the watchdog timer so that it now produces a timer that doesn't reload--since this is pointless for a watchdog. Finally, connects a reset line to the DMA, to make certain that resetting the CPU will also reset any ongoing DMA operation.	dgisselq	2917d 18h	/xulalx25soc/trunk/rtl/
67	Simplifies logic, and guarantees that the minimum set value will always produce an int. For example, if the count was X before, setting X-1 wouldn't produce an interrupt since it had passed. Now it produces an interrupt, and keeps the next interrupt valid.	dgisselq	2917d 18h	/xulalx25soc/trunk/rtl/
66	Simplified logic (barely).	dgisselq	2917d 18h	/xulalx25soc/trunk/rtl/

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Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] - Rev 100

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