| Rev |
Log message |
Author |
Age |
Path |
| 114 |
Added ZipBones to the list of dependencies, so this will (should) build
properly for the XULA9 as well as the XULA25. |
dgisselq |
2882d 00h |
/xulalx25soc/trunk/rtl/ |
| 113 |
Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache. |
dgisselq |
2882d 00h |
/xulalx25soc/trunk/rtl/ |
| 109 |
This continues the updates to the wishbone-uart conversion. It fixes several
bugs within wbuexec, and pipelines the compression scheme. Further, the
read codeword was adjusted so that a read of 8 can be requested with six-bits,
rather than requiring 12. Likewise, the dependence upon the read of 8 on
incrementing the address pointer has been removed. All told, the design
builds for a 200MHz Artix-7, and it has been tested with the CMod-S6. (Writing
flash seems to be one of the most comprehensive tests ...) |
dgisselq |
2890d 08h |
/xulalx25soc/trunk/rtl/ |
| 108 |
Minor documentation updates. |
dgisselq |
2890d 18h |
/xulalx25soc/trunk/rtl/ |
| 106 |
Minor, inconsequential changes. |
dgisselq |
2890d 18h |
/xulalx25soc/trunk/rtl/ |
| 102 |
Updated documentation. The documentation for these now also reflects that
these were drawn from an FPGA Library project, that is shared among many
FPGA builds. |
dgisselq |
2890d 18h |
/xulalx25soc/trunk/rtl/ |
| 101 |
Fixed the `defines at the top so that this can be built without any CPU.
This was then used to measure the impact of the CPU on the entire build, as
you could now build with no CPU, and then with a CPU to compare. |
dgisselq |
2890d 18h |
/xulalx25soc/trunk/rtl/ |
| 100 |
Includes updates so this can run at higher clocks speeds within an FPGA. |
dgisselq |
2890d 18h |
/xulalx25soc/trunk/rtl/ |
| 99 |
Includes high-speed updates. rxuart and txuart will now run at 200MHz on
an Artix-7, so should not impact timing (any more) on the XuLA platform. |
dgisselq |
2890d 19h |
/xulalx25soc/trunk/rtl/ |
| 98 |
Updated copyright notices for the new year, to reflect that changes have been
made in 2016. |
dgisselq |
2890d 19h |
/xulalx25soc/trunk/rtl/ |
| 90 |
Reads and writes to the SD over SPI port now work. The card appears, as of now,
to be fully functional. |
dgisselq |
2913d 23h |
/xulalx25soc/trunk/rtl/ |
| 89 |
Bug fixes, following the adf_ce logic combining ALU/DIVIDE/FPU pipeline logic
into one register, this fixes that logic so that instructions without their
condition fulfilled are still "executed" and marked as done. |
dgisselq |
2913d 23h |
/xulalx25soc/trunk/rtl/ |
| 88 |
Adjusted copyright date. |
dgisselq |
2913d 23h |
/xulalx25soc/trunk/rtl/ |
| 87 |
Placed the interrupt into the carry chain for less logic area. |
dgisselq |
2913d 23h |
/xulalx25soc/trunk/rtl/ |
| 86 |
Fine tuning the `defines, so that you can build pipelined without pipelined
bus access and so forth. |
dgisselq |
2913d 23h |
/xulalx25soc/trunk/rtl/ |
| 85 |
First version of the SD-SPI interface, with partial functionality. (No the
empty link that was here before.) |
dgisselq |
2917d 20h |
/xulalx25soc/trunk/rtl/ |
| 84 |
First part of switching to proper sdspi.v, and not just the link. |
dgisselq |
2917d 20h |
/xulalx25soc/trunk/rtl/ |
| 83 |
Fixes a bug in the LX9 build whereby the flash was never ever granted permission
to use the SPI port. |
dgisselq |
2918d 23h |
/xulalx25soc/trunk/rtl/ |
| 74 |
Adds the SD-card capability, and connects the debug wires to/from the uartdev
in case it needs to be debugged. |
dgisselq |
2919d 19h |
/xulalx25soc/trunk/rtl/ |
| 73 |
Simplified logic. |
dgisselq |
2919d 19h |
/xulalx25soc/trunk/rtl/ |
