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[/] [xulalx25soc/] [trunk/] [rtl/] - Rev 29

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Rev Log message Author Age Path
27 Bug fix: the last_state register now correctly reflects all 5-bits of the state
machine. (Useful when detecting lockups ...)		 dgisselq 3030d 09h /xulalx25soc/trunk/rtl/
26 Some bug fixes, and the long jump early branching integration. dgisselq 3030d 09h /xulalx25soc/trunk/rtl/
23 This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update.		 dgisselq 3038d 19h /xulalx25soc/trunk/rtl/
21 Files, not links, to replace what were once broken links in this project. dgisselq 3091d 18h /xulalx25soc/trunk/rtl/
19 Step one in fixing soft link poblems. The following files were soft links,
and not brought into the svn repository properly. They'll be replaced in the
next update with their full sources.		 dgisselq 3091d 19h /xulalx25soc/trunk/rtl/
18 Got the bitfile back up to speed at 80 MHz. dgisselq 3095d 09h /xulalx25soc/trunk/rtl/
14 Quick bug fix. dgisselq 3097d 05h /xulalx25soc/trunk/rtl/
9 Bug fixes, optimizations, etc. as part of building for an actual hardware
implementation. Most notably, the speed was lowered from 80MHz down to
76 MHz.		 dgisselq 3097d 08h /xulalx25soc/trunk/rtl/
8 Added an interface description to the comments at the top of the file. dgisselq 3099d 17h /xulalx25soc/trunk/rtl/
7 Mostly minor changes. Fixed the legal copyright statement in the UART files,
adjusted some comments, and made sure that the zipdbg program contained all
the latest features from our Vault.		 dgisselq 3099d 18h /xulalx25soc/trunk/rtl/
6 Initial file load, likely to be buggy, but the initial load nonetheless. dgisselq 3100d 04h /xulalx25soc/trunk/rtl/
3 dgisselq 3100d 04h /xulalx25soc/trunk/rtl/
2 A very first, albeit incomplete, build. dgisselq 3100d 04h /xulalx25soc/trunk/rtl/

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