| Rev |
Log message |
Author |
Age |
Path |
| 59 |
Simplified logic. |
dgisselq |
2931d 08h |
/xulalx25soc/trunk/rtl/ |
| 58 |
Bug fix: the UART can now be reconfigured post-boot without a BREAK condition. |
dgisselq |
2931d 08h |
/xulalx25soc/trunk/rtl/ |
| 57 |
Fixed the TX/RX addresses so that they match the documentation: TX first, then
RX. |
dgisselq |
2939d 08h |
/xulalx25soc/trunk/rtl/ |
| 56 |
Brings code in line with the OpenCores core: parameterizes the reload value,
and the number of bits in the timer. |
dgisselq |
2939d 08h |
/xulalx25soc/trunk/rtl/ |
| 55 |
Updated copyright notice. |
dgisselq |
2939d 08h |
/xulalx25soc/trunk/rtl/ |
| 54 |
Updated copyright notice. |
dgisselq |
2939d 08h |
/xulalx25soc/trunk/rtl/ |
| 52 |
This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change. |
dgisselq |
2979d 09h |
/xulalx25soc/trunk/rtl/ |
| 51 |
Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags. |
dgisselq |
2989d 07h |
/xulalx25soc/trunk/rtl/ |
| 50 |
Updates to fix some broken early branching code, both in idecode and pfcache. |
dgisselq |
2998d 09h |
/xulalx25soc/trunk/rtl/ |
| 48 |
Cleaned up the documentation a touch. It no longer reads like the bugs I used
to debug are still being debugged ... |
dgisselq |
3009d 11h |
/xulalx25soc/trunk/rtl/ |
| 46 |
This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles. |
dgisselq |
3009d 11h |
/xulalx25soc/trunk/rtl/ |
| 45 |
Minor cosmetic change, eliminates a warning in Xilinx's XISE but offers no
functional difference. |
dgisselq |
3013d 07h |
/xulalx25soc/trunk/rtl/ |
| 44 |
NELM parameter adjusted to reflect the maximum number of lines the compressed
scope can handle: 31, not 32. |
dgisselq |
3013d 07h |
/xulalx25soc/trunk/rtl/ |
| 43 |
Commentary changes only, no substance. |
dgisselq |
3013d 07h |
/xulalx25soc/trunk/rtl/ |
| 39 |
An attempt at a bugfix. We'll see if this works any better downstream. |
dgisselq |
3016d 14h |
/xulalx25soc/trunk/rtl/ |
| 37 |
These fixes were necessary to get the SDRAM into a working simulation
capability. It is finally what it was supposed to be: cycle accurate. Sadly,
to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
a problem with external input clocking in Verilator. This fixes it--but its
a Verilator only change--to rtl/wbsdram.v that is.) |
dgisselq |
3017d 11h |
/xulalx25soc/trunk/rtl/ |
| 34 |
Bug fix: This sets as a positive voltage bias (not negative) the maximum
value of 0x07fff, where as the negative maximum value of 0x08000 properly
(now) reflects nearly ground--as one would desire. (Last time around I had
these backwards.) |
dgisselq |
3021d 08h |
/xulalx25soc/trunk/rtl/ |
| 32 |
Just noticed that the timer was fixed on this. This change adjusts the
timer to support audio at a user selectable rate. |
dgisselq |
3021d 10h |
/xulalx25soc/trunk/rtl/ |
| 31 |
A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25. |
dgisselq |
3021d 10h |
/xulalx25soc/trunk/rtl/ |
| 27 |
Bug fix: the last_state register now correctly reflects all 5-bits of the state
machine. (Useful when detecting lockups ...) |
dgisselq |
3022d 11h |
/xulalx25soc/trunk/rtl/ |
