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[/] [xulalx25soc/] [trunk/] [rtl/] - Rev 68

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68 Fixes the debug ack line, so it no longer acks when there isn't a dbg_stb.
Fixed the multiply option parameter, so it sets a 3-clock multiply properly.
Adjusted the watchdog timer so that it now produces a timer that doesn't
reload--since this is pointless for a watchdog. Finally, connects a reset
line to the DMA, to make certain that resetting the CPU will also reset any
ongoing DMA operation.		 dgisselq 2915d 17h /xulalx25soc/trunk/rtl/
67 Simplifies logic, and guarantees that the minimum set value will always
produce an int. For example, if the count was X before, setting X-1 wouldn't
produce an interrupt since it had passed. Now it produces an interrupt, and
keeps the next interrupt valid.		 dgisselq 2915d 17h /xulalx25soc/trunk/rtl/
66 Simplified logic (barely). dgisselq 2915d 18h /xulalx25soc/trunk/rtl/
65 Makes the auto-reload feature a parameterized (generic) feature, so the same
code will work for both auto-reloadable and non-autoreloadable (i.e. watchdog)
timers.		 dgisselq 2915d 18h /xulalx25soc/trunk/rtl/
64 First (verified) working version. dgisselq 2915d 18h /xulalx25soc/trunk/rtl/
63 Simplified logic. dgisselq 2915d 18h /xulalx25soc/trunk/rtl/
62 Removed the pipe logic from the non-pipelined version, and made the NOOP a
specific ALU instruction so that the PC is always properly updated.		 dgisselq 2915d 18h /xulalx25soc/trunk/rtl/
61 Fixed the timing control wires: busy and valid will never both be true. Busy
will be true (now) until valid is asserted, and busy will never not be
asserted until valid is true.		 dgisselq 2915d 18h /xulalx25soc/trunk/rtl/
60 LONG_MPY upgrade. This is part of swapping out the LDIHI instruction for a
MPY, and the MPYS and MPYU instructions for MPYSHI and MPYUHI respectively.		 dgisselq 2915d 18h /xulalx25soc/trunk/rtl/
59 Simplified logic. dgisselq 2915d 18h /xulalx25soc/trunk/rtl/
58 Bug fix: the UART can now be reconfigured post-boot without a BREAK condition. dgisselq 2915d 18h /xulalx25soc/trunk/rtl/
57 Fixed the TX/RX addresses so that they match the documentation: TX first, then
RX.		 dgisselq 2923d 17h /xulalx25soc/trunk/rtl/
56 Brings code in line with the OpenCores core: parameterizes the reload value,
and the number of bits in the timer.		 dgisselq 2923d 17h /xulalx25soc/trunk/rtl/
55 Updated copyright notice. dgisselq 2923d 18h /xulalx25soc/trunk/rtl/
54 Updated copyright notice. dgisselq 2923d 18h /xulalx25soc/trunk/rtl/
52 This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change.		 dgisselq 2963d 18h /xulalx25soc/trunk/rtl/
51 Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags.		 dgisselq 2973d 16h /xulalx25soc/trunk/rtl/
50 Updates to fix some broken early branching code, both in idecode and pfcache. dgisselq 2982d 19h /xulalx25soc/trunk/rtl/
48 Cleaned up the documentation a touch. It no longer reads like the bugs I used
to debug are still being debugged ...		 dgisselq 2993d 21h /xulalx25soc/trunk/rtl/
46 This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles.		 dgisselq 2993d 21h /xulalx25soc/trunk/rtl/

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