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[/] [xulalx25soc/] [trunk/] [rtl/] - Rev 88

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Rev	Log message	Author	Age	Path
88	Adjusted copyright date.	dgisselq	2910d 17h	/xulalx25soc/trunk/rtl/
87	Placed the interrupt into the carry chain for less logic area.	dgisselq	2910d 17h	/xulalx25soc/trunk/rtl/
86	Fine tuning the `defines, so that you can build pipelined without pipelined bus access and so forth.	dgisselq	2910d 17h	/xulalx25soc/trunk/rtl/
85	First version of the SD-SPI interface, with partial functionality. (No the empty link that was here before.)	dgisselq	2914d 14h	/xulalx25soc/trunk/rtl/
84	First part of switching to proper sdspi.v, and not just the link.	dgisselq	2914d 14h	/xulalx25soc/trunk/rtl/
83	Fixes a bug in the LX9 build whereby the flash was never ever granted permission to use the SPI port.	dgisselq	2915d 18h	/xulalx25soc/trunk/rtl/
74	Adds the SD-card capability, and connects the debug wires to/from the uartdev in case it needs to be debugged.	dgisselq	2916d 14h	/xulalx25soc/trunk/rtl/
73	Simplified logic.	dgisselq	2916d 14h	/xulalx25soc/trunk/rtl/
72	Sets XULA25 as the default.	dgisselq	2916d 14h	/xulalx25soc/trunk/rtl/
71	Needed to play with subtle timing to get this to build. Expect me to play with these two clock numbers more.	dgisselq	2916d 14h	/xulalx25soc/trunk/rtl/
70	Cosmetic (minor) update.	dgisselq	2916d 14h	/xulalx25soc/trunk/rtl/
69	Massive logic simplification. This is also the first (verified) working version.	dgisselq	2916d 14h	/xulalx25soc/trunk/rtl/
68	Fixes the debug ack line, so it no longer acks when there isn't a dbg_stb. Fixed the multiply option parameter, so it sets a 3-clock multiply properly. Adjusted the watchdog timer so that it now produces a timer that doesn't reload--since this is pointless for a watchdog. Finally, connects a reset line to the DMA, to make certain that resetting the CPU will also reset any ongoing DMA operation.	dgisselq	2916d 14h	/xulalx25soc/trunk/rtl/
67	Simplifies logic, and guarantees that the minimum set value will always produce an int. For example, if the count was X before, setting X-1 wouldn't produce an interrupt since it had passed. Now it produces an interrupt, and keeps the next interrupt valid.	dgisselq	2916d 14h	/xulalx25soc/trunk/rtl/
66	Simplified logic (barely).	dgisselq	2916d 14h	/xulalx25soc/trunk/rtl/
65	Makes the auto-reload feature a parameterized (generic) feature, so the same code will work for both auto-reloadable and non-autoreloadable (i.e. watchdog) timers.	dgisselq	2916d 14h	/xulalx25soc/trunk/rtl/
64	First (verified) working version.	dgisselq	2916d 14h	/xulalx25soc/trunk/rtl/
63	Simplified logic.	dgisselq	2916d 14h	/xulalx25soc/trunk/rtl/
62	Removed the pipe logic from the non-pipelined version, and made the NOOP a specific ALU instruction so that the PC is always properly updated.	dgisselq	2916d 14h	/xulalx25soc/trunk/rtl/
61	Fixed the timing control wires: busy and valid will never both be true. Busy will be true (now) until valid is asserted, and busy will never not be asserted until valid is true.	dgisselq	2916d 14h	/xulalx25soc/trunk/rtl/

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[/] [xulalx25soc/] [trunk/] [rtl/] - Rev 88

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