| Rev |
Log message |
Author |
Age |
Path |
| 117 |
Updates, to include new README and bench/cpp/Makefile that doesnt depend upon
a static VERILATOR_ROOT location. |
dgisselq |
2797d 21h |
/xulalx25soc/trunk/rtl/cpu/ |
| 113 |
Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache. |
dgisselq |
2890d 22h |
/xulalx25soc/trunk/rtl/cpu/ |
| 98 |
Updated copyright notices for the new year, to reflect that changes have been
made in 2016. |
dgisselq |
2899d 17h |
/xulalx25soc/trunk/rtl/cpu/ |
| 89 |
Bug fixes, following the adf_ce logic combining ALU/DIVIDE/FPU pipeline logic
into one register, this fixes that logic so that instructions without their
condition fulfilled are still "executed" and marked as done. |
dgisselq |
2922d 21h |
/xulalx25soc/trunk/rtl/cpu/ |
| 87 |
Placed the interrupt into the carry chain for less logic area. |
dgisselq |
2922d 21h |
/xulalx25soc/trunk/rtl/cpu/ |
| 86 |
Fine tuning the `defines, so that you can build pipelined without pipelined
bus access and so forth. |
dgisselq |
2922d 21h |
/xulalx25soc/trunk/rtl/cpu/ |
| 73 |
Simplified logic. |
dgisselq |
2928d 17h |
/xulalx25soc/trunk/rtl/cpu/ |
| 72 |
Sets XULA25 as the default. |
dgisselq |
2928d 17h |
/xulalx25soc/trunk/rtl/cpu/ |
| 70 |
Cosmetic (minor) update. |
dgisselq |
2928d 17h |
/xulalx25soc/trunk/rtl/cpu/ |
| 69 |
Massive logic simplification. This is also the first (verified) working
version. |
dgisselq |
2928d 17h |
/xulalx25soc/trunk/rtl/cpu/ |
| 68 |
Fixes the debug ack line, so it no longer acks when there isn't a dbg_stb.
Fixed the multiply option parameter, so it sets a 3-clock multiply properly.
Adjusted the watchdog timer so that it now produces a timer that doesn't
reload--since this is pointless for a watchdog. Finally, connects a reset
line to the DMA, to make certain that resetting the CPU will also reset any
ongoing DMA operation. |
dgisselq |
2928d 18h |
/xulalx25soc/trunk/rtl/cpu/ |
| 67 |
Simplifies logic, and guarantees that the minimum set value will always
produce an int. For example, if the count was X before, setting X-1 wouldn't
produce an interrupt since it had passed. Now it produces an interrupt, and
keeps the next interrupt valid. |
dgisselq |
2928d 18h |
/xulalx25soc/trunk/rtl/cpu/ |
| 66 |
Simplified logic (barely). |
dgisselq |
2928d 18h |
/xulalx25soc/trunk/rtl/cpu/ |
| 65 |
Makes the auto-reload feature a parameterized (generic) feature, so the same
code will work for both auto-reloadable and non-autoreloadable (i.e. watchdog)
timers. |
dgisselq |
2928d 18h |
/xulalx25soc/trunk/rtl/cpu/ |
| 62 |
Removed the pipe logic from the non-pipelined version, and made the NOOP a
specific ALU instruction so that the PC is always properly updated. |
dgisselq |
2928d 18h |
/xulalx25soc/trunk/rtl/cpu/ |
| 61 |
Fixed the timing control wires: busy and valid will never both be true. Busy
will be true (now) until valid is asserted, and busy will never not be
asserted until valid is true. |
dgisselq |
2928d 18h |
/xulalx25soc/trunk/rtl/cpu/ |
| 60 |
LONG_MPY upgrade. This is part of swapping out the LDIHI instruction for a
MPY, and the MPYS and MPYU instructions for MPYSHI and MPYUHI respectively. |
dgisselq |
2928d 18h |
/xulalx25soc/trunk/rtl/cpu/ |
| 52 |
This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change. |
dgisselq |
2976d 18h |
/xulalx25soc/trunk/rtl/cpu/ |
| 51 |
Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags. |
dgisselq |
2986d 16h |
/xulalx25soc/trunk/rtl/cpu/ |
| 50 |
Updates to fix some broken early branching code, both in idecode and pfcache. |
dgisselq |
2995d 19h |
/xulalx25soc/trunk/rtl/cpu/ |
