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[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] - Rev 45

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Rev Log message Author Age Path
45 Minor cosmetic change, eliminates a warning in Xilinx's XISE but offers no
functional difference.		 dgisselq 3007d 02h /xulalx25soc/trunk/rtl/cpu/
31 A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25.		 dgisselq 3015d 05h /xulalx25soc/trunk/rtl/cpu/
26 Some bug fixes, and the long jump early branching integration. dgisselq 3016d 06h /xulalx25soc/trunk/rtl/cpu/
23 This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update.		 dgisselq 3024d 15h /xulalx25soc/trunk/rtl/cpu/
21 Files, not links, to replace what were once broken links in this project. dgisselq 3077d 15h /xulalx25soc/trunk/rtl/cpu/
19 Step one in fixing soft link poblems. The following files were soft links,
and not brought into the svn repository properly. They'll be replaced in the
next update with their full sources.		 dgisselq 3077d 15h /xulalx25soc/trunk/rtl/cpu/
2 A very first, albeit incomplete, build. dgisselq 3086d 01h /xulalx25soc/trunk/rtl/cpu/

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