| Rev |
Log message |
Author |
Age |
Path |
| 60 |
LONG_MPY upgrade. This is part of swapping out the LDIHI instruction for a
MPY, and the MPYS and MPYU instructions for MPYSHI and MPYUHI respectively. |
dgisselq |
3078d 06h |
/xulalx25soc/trunk/rtl/cpu/ |
| 52 |
This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change. |
dgisselq |
3126d 06h |
/xulalx25soc/trunk/rtl/cpu/ |
| 51 |
Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags. |
dgisselq |
3136d 05h |
/xulalx25soc/trunk/rtl/cpu/ |
| 50 |
Updates to fix some broken early branching code, both in idecode and pfcache. |
dgisselq |
3145d 07h |
/xulalx25soc/trunk/rtl/cpu/ |
| 46 |
This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles. |
dgisselq |
3156d 09h |
/xulalx25soc/trunk/rtl/cpu/ |
| 45 |
Minor cosmetic change, eliminates a warning in Xilinx's XISE but offers no
functional difference. |
dgisselq |
3160d 05h |
/xulalx25soc/trunk/rtl/cpu/ |
| 31 |
A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25. |
dgisselq |
3168d 08h |
/xulalx25soc/trunk/rtl/cpu/ |
| 26 |
Some bug fixes, and the long jump early branching integration. |
dgisselq |
3169d 09h |
/xulalx25soc/trunk/rtl/cpu/ |
| 23 |
This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update. |
dgisselq |
3177d 19h |
/xulalx25soc/trunk/rtl/cpu/ |
| 21 |
Files, not links, to replace what were once broken links in this project. |
dgisselq |
3230d 18h |
/xulalx25soc/trunk/rtl/cpu/ |
| 19 |
Step one in fixing soft link poblems. The following files were soft links,
and not brought into the svn repository properly. They'll be replaced in the
next update with their full sources. |
dgisselq |
3230d 18h |
/xulalx25soc/trunk/rtl/cpu/ |
| 2 |
A very first, albeit incomplete, build. |
dgisselq |
3239d 04h |
/xulalx25soc/trunk/rtl/cpu/ |
