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[/] [xulalx25soc/] [trunk/] [sw/] - Rev 45

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Rev Log message Author Age Path
42 Minor changes. dgisselq 2997d 18h /xulalx25soc/trunk/sw/
41 Bug fix. This was preventing dumpsdram from accurately reading back what
had been written to the RAM earlier.		 dgisselq 2997d 18h /xulalx25soc/trunk/sw/
40 This adds to dumpsdram the capability to run over a port, such as with
busmaster_tb.		 dgisselq 2999d 05h /xulalx25soc/trunk/sw/
38 Updated to remove the build dependence upon ZipCPU. dgisselq 3001d 04h /xulalx25soc/trunk/sw/
33 Oops -- the audio was wired audio first then the interrupt controller, not
the other way around. This adjusts regdefs to match what's on the chip.		 dgisselq 3005d 21h /xulalx25soc/trunk/sw/
31 A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25.		 dgisselq 3005d 21h /xulalx25soc/trunk/sw/
30 Bug fixes. In particular, this fixes a segmentation violation. dgisselq 3006d 01h /xulalx25soc/trunk/sw/
29 This adds a vastly updated and superious ziprun capability to the repository.
ziprun now accepts ELF program files *only*, reads them, and places them onto
the board. This includes the ability, within the ELF file, of specifying
whether or not the data is sent to block ram, SD ram, or Flash, as well as
the ability of specifying the initial address. (Of course, that's a one time
thing--to always have the same initial address, set the address in
rtl/busmaster.v)		 dgisselq 3006d 17h /xulalx25soc/trunk/sw/
28 Oops--two files needed by zipdbg weren't originally placed in the directory. dgisselq 3006d 22h /xulalx25soc/trunk/sw/
25 Fixing compile time warnings. dgisselq 3006d 22h /xulalx25soc/trunk/sw/
24 Added the #define necessary to enable (and clear) SCOPE interrupts. dgisselq 3012d 20h /xulalx25soc/trunk/sw/
17 Some basic updates, to include adding in a missing file (zipstate). Most of
these updates include making sure that the XuLA2 device can be accessed via
the USB. (Prior versions accessed the FPGA via serial port or network ...)		 dgisselq 3071d 22h /xulalx25soc/trunk/sw/
13 This version is now working. (It probably would've worked before, but
everything is now working.)		 dgisselq 3073d 18h /xulalx25soc/trunk/sw/
11 Getting software up and running on the board for the first time. (Not there
yet, but I think these items have now proven themselves.)		 dgisselq 3073d 20h /xulalx25soc/trunk/sw/
7 Mostly minor changes. Fixed the legal copyright statement in the UART files,
adjusted some comments, and made sure that the zipdbg program contained all
the latest features from our Vault.		 dgisselq 3076d 06h /xulalx25soc/trunk/sw/
5 Initial software version, in support of the project. At this point, they are
provided with no guarantees that they work. (They did use to work--on an older
build, but I haven't been able to verify that they work with this newer build
yet.)		 dgisselq 3076d 16h /xulalx25soc/trunk/sw/

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