URL https://opencores.org/ocsvn/y80e/y80e/trunk

Subversion Repositories y80e

[/] [y80e/] - Rev 13

Rev	Log message	Author	Age	Path
13	Updated instruction set table	bsa	1867d 12h	/y80e/
12	Added SVN property eol-style:native	bsa	1867d 13h	/y80e/
11	Added memory initialization files for testbench	bsa	1867d 13h	/y80e/
10	Added mnemonic list	bsa	4192d 00h	/y80e/
9		bsa	4192d 13h	/y80e/
8	Added support for Zilog eZ80 instructions Added support for all eZ80 instructions which works in non-ADL mode (i.e. 16-bit address mode only).	bsa	4192d 13h	/y80e/
7		bsa	4192d 13h	/y80e/
6	Added support for Z180 instructions	bsa	4192d 13h	/y80e/
5	This version is compatible with Zilog Z80 CPU Instructions RES/SET (ii+d),r is unsupported Nonstandard NEG and others ED-prefixed are also unsupported	bsa	4192d 13h	/y80e/
4	Added support for commonly used Z80 undocumented instructions This instructions includes: - operations with halfs of IX and IY registers - undocumented shift instruction SLI (or SLL - Shift Left Logically) Also added emulation of R register	bsa	4192d 13h	/y80e/
3	Complete Y80 implementation. This version of CPU is described in book 'Microprocessor Design Using Verilog HDL' by Monte Dalryple from Systemyde. control.v file completed by me and author of CPU permits me to publish this project.	bsa	4192d 13h	/y80e/
2	Completed Y80 from Systemyde w/o anything else	bsa	4192d 13h	/y80e/
1	The project and the structure was created	root	4193d 02h	/y80e/