| Rev |
Log message |
Author |
Age |
Path |
| 98 |
Added justed longjump instructions from the previous (not used, broken)
functionality to the new LOD (PC),PC functionality. |
dgisselq |
3172d 09h |
/zipcpu/ |
| 97 |
Added longjump instructions. |
dgisselq |
3172d 09h |
/zipcpu/ |
| 96 |
Added the longjump functionality, so that the assembler will properly assemble
instructions to arbitrary 32-bit addresses. |
dgisselq |
3172d 09h |
/zipcpu/ |
| 95 |
Fixed a bug whereby a mistaken code for CLR was masking a valid LDI of a large
integer value. |
dgisselq |
3174d 15h |
/zipcpu/ |
| 94 |
These changes make it possible to build binutils-2.25/ here in this
directory. "make binutils" should be all that is necessary to build the
entire binutils package for the Zip CPU.
The default configure script, run from gas-script.sh below, will build and
install these utilities in an install/ subdirectory made below sw/. |
dgisselq |
3199d 13h |
/zipcpu/ |
| 93 |
A BINUTILS BACKEND IS NOW AVAILABLE!!!! |
dgisselq |
3207d 10h |
/zipcpu/ |
| 92 |
Adjustments made to match the simplified early branching. |
dgisselq |
3207d 10h |
/zipcpu/ |
| 91 |
Minor updates. |
dgisselq |
3207d 10h |
/zipcpu/ |
| 90 |
Removed MOV x(PC),PC from the list of possible early branching instructions.
ADD X,PC and LDI X,PC are now the only recognized early branching instructions.
This was done to spare logic, although I don't think I spared more than a
LUT or two. |
dgisselq |
3207d 10h |
/zipcpu/ |
| 89 |
Minor changes, to include making default branching an ADD.[condition] X,PC
instruction, rather than allowing both MOV X(PC),PC and ADD X,PC instructions.
Further zopcodes.cpp contains several bug fixes. |
dgisselq |
3207d 11h |
/zipcpu/ |
| 88 |
Eliminated some warnings. The div fixes were to simplify the logic, even though
the result is less readable ... |
dgisselq |
3231d 10h |
/zipcpu/ |
| 87 |
Adjusted the operator input line to reflect actual logic inputs, rather
than the registered inputs which may have been out of date. (Indeed, they
were out of date for the bug I was chasing and fixed ...) |
dgisselq |
3233d 09h |
/zipcpu/ |
| 86 |
Removed the requirement to have the dev.scope.cpu hardware defined outside
of the Zip CPU (it was defined in another project). This was causing a bus
error in the simulator (which it should have), but taking it out fixes things
in the simulator (while removing capability from one special piece of H/W). |
dgisselq |
3233d 09h |
/zipcpu/ |
| 85 |
Minor update/correction to operand B definition. |
dgisselq |
3233d 09h |
/zipcpu/ |
| 84 |
Minor updates. |
dgisselq |
3233d 09h |
/zipcpu/ |
| 83 |
Added a flag to indicate whether an exception took place on the first
or second half of a VLIW instruction--will be zero in non-VLIW mode,
equivalent to the second half of the instruction having caused the
exception. (Expect these flags to be reordered some time in the future into
a less haphazard ordering ...)
Vastly simplified the pipeline logic, primarily for op_stall, but also touched
opA and opB. (Trying to fit within timing on Spartan 6 ...)
Changed division instruction to include a reset on clear_pipeline, to make
certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is
true. |
dgisselq |
3233d 09h |
/zipcpu/ |
| 82 |
Found and (I hope) fixed a nasty bug that would send the prefetch into an
endless loop whenever you jumped to an instruction at the last location
in an unloaded cache line. |
dgisselq |
3233d 09h |
/zipcpu/ |
| 81 |
Trying to clean up ISE generated warnings. |
dgisselq |
3233d 09h |
/zipcpu/ |
| 80 |
Bug fix: declared the (combined) multiply to be signed again. Also
changed the name of the generate'd for block, to keep ISE from complaining. |
dgisselq |
3233d 09h |
/zipcpu/ |
| 79 |
Adjusted the opcodes for NOOP, BREAK, and LOCK. |
dgisselq |
3237d 13h |
/zipcpu/ |
