OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [asm/] - Rev 50

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
50 Dhrystone benchmark updates--added the copyright notice. (Oops!) dgisselq 3288d 14h /zipcpu/trunk/bench/asm/
42 Oops -- forgot to add the stack. dgisselq 3288d 14h /zipcpu/trunk/bench/asm/
41 Assembly file for the Dhrystone benchmark added. dgisselq 3288d 14h /zipcpu/trunk/bench/asm/
40 Quick update, updates the assembly for the new version of the assembler. dgisselq 3288d 14h /zipcpu/trunk/bench/asm/
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 3300d 22h /zipcpu/trunk/bench/asm/
12 Bunch of changes while trying to get a hello world program:
1. Right shifts by 32 or more now result in zero, or all of the top bit in the
case of ASRs.
2. zdump now properly includes addresses with dumped lines.
3. zparser now properly handles immediate values via the .DAT instruction.
dgisselq 3354d 15h /zipcpu/trunk/bench/asm/
11 This version works on an FPGA!!!

(Or at least the wdt.S program passes ...)
dgisselq 3355d 00h /zipcpu/trunk/bench/asm/
10 Here's the watchdog timer code, as well as some pictures of the register
set.
dgisselq 3355d 13h /zipcpu/trunk/bench/asm/
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 3356d 14h /zipcpu/trunk/bench/asm/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.