OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [doc/] [src/] - Rev 130

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
92 Adjustments made to match the simplified early branching. dgisselq 3061d 21h /zipcpu/trunk/doc/src/
73 Documentations updates. dgisselq 3092d 23h /zipcpu/trunk/doc/src/
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.		 dgisselq 3099d 04h /zipcpu/trunk/doc/src/
68 Updated specification, includes well illustrated pipeline discussion. dgisselq 3134d 04h /zipcpu/trunk/doc/src/
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.		 dgisselq 3183d 01h /zipcpu/trunk/doc/src/
37 Fixed some minor spelling errors. dgisselq 3191d 18h /zipcpu/trunk/doc/src/
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.		 dgisselq 3192d 07h /zipcpu/trunk/doc/src/
33 Finally finished a first draft of the full specification! dgisselq 3221d 00h /zipcpu/trunk/doc/src/
32 Updated the document to match the most recent changes to the CPU. Specifically,
these include the re-instatement of the full SUB command with immediate offset,
and ... others I cannot remember.

The new document also describes what conditions create pipeline stalls,
together with how many cycles each stall condition will create.		 dgisselq 3221d 07h /zipcpu/trunk/doc/src/
24 Lots more changes to the spec. It's still not done, but it is more complete
than before.		 dgisselq 3224d 08h /zipcpu/trunk/doc/src/
23 Oops -- left some portions of the RTC Clock spec in with the ZIP CPU spec.
These were quickly removed.		 dgisselq 3226d 04h /zipcpu/trunk/doc/src/
22 dgisselq 3226d 04h /zipcpu/trunk/doc/src/
21 This update adds an incomplete version of the specification for the chip.
I ned to come back to this and do a lot more writing, but it is a start.		 dgisselq 3226d 04h /zipcpu/trunk/doc/src/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.