| Rev |
Log message |
Author |
Age |
Path |
| 209 |
8b bytes, + formal verification throughout + dcache |
dgisselq |
2058d 14h |
/zipcpu/trunk/rtl/peripherals/ |
| 201 |
RTL files for the 8-bit capable ZipCPU. |
dgisselq |
2798d 00h |
/zipcpu/trunk/rtl/peripherals/ |
| 182 |
Bug fix for fast memories. This now works for memories with single cycle
latencies. |
dgisselq |
2972d 21h |
/zipcpu/trunk/rtl/peripherals/ |
| 181 |
Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well. |
dgisselq |
2972d 21h |
/zipcpu/trunk/rtl/peripherals/ |
| 160 |
Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.) |
dgisselq |
3065d 17h |
/zipcpu/trunk/rtl/peripherals/ |
| 144 |
Makes the auto-reload capability a configuration option, and fills out the
reset so that it is properly implemented. |
dgisselq |
3098d 16h |
/zipcpu/trunk/rtl/peripherals/ |
| 88 |
Eliminated some warnings. The div fixes were to simplify the logic, even though
the result is less readable ... |
dgisselq |
3227d 19h |
/zipcpu/trunk/rtl/peripherals/ |
| 69 |
This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture. |
dgisselq |
3241d 02h |
/zipcpu/trunk/rtl/peripherals/ |
| 56 |
Here's a bit of work in progress for getting the Zip CPU working on a XuLA2
board. Many changes include: the existence of a cpudefs.v file to control
what "options" are included in the ZipCPU build. This allows build control
to be separated from the project directory (one build for a XuLA2 board,
another for a Basys-3 development board). Other changes have made things
perhaps harder to read, but they get rid of warnings from XST.
A big change was the addition of the (* ram_style="distributed" *) comment
for the register set. This was necessary to keep XST from inferring a block
RAM and breaking the logic that was supposed to take place between a register
read and when it was used. |
dgisselq |
3312d 04h |
/zipcpu/trunk/rtl/peripherals/ |
| 48 |
Files added/updated to get Dhrystone benchmark to work. Several fixes
to the CPU in the process, 'cause it wasn't working. Stall-less ALU
ops now work better, to include grabbing the memory result as it comes out
of the memory unit and placing it straight into either ALU or memory unit
for the next instruction. |
dgisselq |
3321d 20h |
/zipcpu/trunk/rtl/peripherals/ |
| 36 |
*Lots* of changes to increase processing speed and remove pipeline stalls.
Removed the useless flash cache, replacing it with a proper DMA controller.
"make test" in the main directory now runs a test program in Verilator and
reports on the results. |
dgisselq |
3334d 05h |
/zipcpu/trunk/rtl/peripherals/ |
| 9 |
This checkin is the result of a watchdog timer test, and everything it took
to get the watchdog timer working. The timer function was simplified,
although it now uses a touch more resources--being able to count down 31
bits instead of 30. The parser was modified, since it couldn't handle
storing to register plus offsets like it was supposed to be able to. The
testbench, zippy_tb, was modified to accept an assembled machine code file
such as I might place on a board to test it.
Lots of work to get it working.
Looking at the files below, it looks like I'll need a second check in to check
in the watchdog timer test itself. |
dgisselq |
3388d 19h |
/zipcpu/trunk/rtl/peripherals/ |
| 2 |
An initial load. No promises of what works or not, but this is where the
project is at. |
dgisselq |
3389d 20h |
/zipcpu/trunk/rtl/peripherals/ |
