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Rev Log message Author Age Path
130 prepared programs for new timing. simont 7730d 19h /
129 updated... simont 7730d 19h /
128 chance idat_ir to 24 bit wide simont 7740d 02h /
127 fix bug (cyc_o and stb_o) simont 7740d 02h /
126 define OC8051_XILINX_RAMB added simont 7740d 02h /
125 update, add prescaler, rclk, tclk. simont 7740d 02h /
124 add support for external rom from xilinx ramb4 simont 7740d 02h /
123 fiz bug iv pcs operation. simont 7741d 22h /
122 deifne OC8051_ROM added simont 7745d 02h /
121 Change pc add value from 23'h to 16'h simont 7745d 02h /
120 defines for pherypherals added simont 7745d 23h /
119 remove signal sbuf_txd [12:11] simont 7746d 03h /
118 change wr_sft to 2 bit wire. simont 7746d 20h /
117 Register oc8051_sfr dato output, add signal wait_data. simont 7746d 20h /
116 change sfr's interface. simont 7748d 21h /
115 change uart to meet timing. simont 7748d 23h /
114 remove t2mod register simont 7752d 02h /
113 signal prsc_ow added. simont 7752d 02h /
112 change timers to meet timing specifications (add divider with 12) simont 7752d 02h /
111 Remove instruction cache and wb_interface simont 7752d 17h /

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