URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 142

Rev	Log message	Author	Age	Path
142	optimize state machine.	simont	7784d 06h	/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7784d 07h	/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7784d 07h	/
139	add aditional alu destination to solve critical path.	simont	7785d 01h	/
138	Change buffering to save one clock per instruction.	simont	7785d 01h	/
137	change to fit xrom.	simont	7785d 06h	/
136	registering outputs.	simont	7785d 06h	/
135	prepared start of receiving if ren is not active.	simont	7791d 05h	/
134	fix bug in case execution of two data dependent instructions.	simont	7791d 05h	/
133	fix bug in substraction.	simont	7791d 08h	/
132	change branch instruction execution (reduse needed clock periods).	simont	7794d 23h	/
131	prepare programs for new timing.	simont	7795d 00h	/
130	prepared programs for new timing.	simont	7795d 00h	/
129	updated...	simont	7795d 00h	/
128	chance idat_ir to 24 bit wide	simont	7804d 07h	/
127	fix bug (cyc_o and stb_o)	simont	7804d 07h	/
126	define OC8051_XILINX_RAMB added	simont	7804d 07h	/
125	update, add prescaler, rclk, tclk.	simont	7804d 07h	/
124	add support for external rom from xilinx ramb4	simont	7804d 07h	/
123	fiz bug iv pcs operation.	simont	7806d 02h	/