URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 144

Rev	Log message	Author	Age	Path
144	chsnge comp.des to des1	simont	7860d 08h	/
143	add wire sub_result, conect it to des_acc and des1.	simont	7860d 08h	/
142	optimize state machine.	simont	7861d 09h	/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7861d 11h	/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7861d 11h	/
139	add aditional alu destination to solve critical path.	simont	7862d 05h	/
138	Change buffering to save one clock per instruction.	simont	7862d 05h	/
137	change to fit xrom.	simont	7862d 10h	/
136	registering outputs.	simont	7862d 10h	/
135	prepared start of receiving if ren is not active.	simont	7868d 09h	/
134	fix bug in case execution of two data dependent instructions.	simont	7868d 09h	/
133	fix bug in substraction.	simont	7868d 12h	/
132	change branch instruction execution (reduse needed clock periods).	simont	7872d 03h	/
131	prepare programs for new timing.	simont	7872d 03h	/
130	prepared programs for new timing.	simont	7872d 03h	/
129	updated...	simont	7872d 03h	/
128	chance idat_ir to 24 bit wide	simont	7881d 11h	/
127	fix bug (cyc_o and stb_o)	simont	7881d 11h	/
126	define OC8051_XILINX_RAMB added	simont	7881d 11h	/
125	update, add prescaler, rclk, tclk.	simont	7881d 11h	/