URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 37

Rev	Log message	Author	Age	Path
37	added signals ack, stb and cyc	simont	8120d 20h	/
36	fix bugs in mode 0	simont	8120d 20h	/
35	design docunemt	simont	8121d 19h	/
34	specification docunemt	simont	8121d 19h	/
33	fix some bugs	simont	8122d 00h	/
32	overflow repaired	simont	8122d 01h	/
31	fix some bugs	simont	8128d 17h	/
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	8131d 23h	/
29	fix some bugs	simont	8132d 00h	/
28	remove syn signal	simont	8132d 00h	/
27	fix some bugs	simont	8132d 00h	/
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	8132d 02h	/
25	divider and multiplier pass test	markom	8132d 21h	/
24	intensively tests all instructions	markom	8133d 02h	/
23	mul & div use 4 clocks	simont	8133d 16h	/
22	fix some bugs	simont	8133d 16h	/
21	mul bug fixed	markom	8133d 21h	/
20	multiplier and divider changed so they complete in 4 cycles	markom	8134d 00h	/
19	combinatorial loop removed	simont	8134d 16h	/
18	rst signal added	simont	8137d 22h	/