OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 39

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
39 added signals ack, stb and cyc simont 8117d 03h /
38 fix some bugs simont 8117d 03h /
37 added signals ack, stb and cyc simont 8117d 03h /
36 fix bugs in mode 0 simont 8117d 03h /
35 design docunemt simont 8118d 01h /
34 specification docunemt simont 8118d 01h /
33 fix some bugs simont 8118d 07h /
32 overflow repaired simont 8118d 07h /
31 fix some bugs simont 8124d 23h /
30 mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32 simont 8128d 06h /
29 fix some bugs simont 8128d 07h /
28 remove syn signal simont 8128d 07h /
27 fix some bugs simont 8128d 07h /
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 8128d 09h /
25 divider and multiplier pass test markom 8129d 03h /
24 intensively tests all instructions markom 8129d 08h /
23 mul & div use 4 clocks simont 8129d 23h /
22 fix some bugs simont 8129d 23h /
21 mul bug fixed markom 8130d 04h /
20 multiplier and divider changed so they complete in 4 cycles markom 8130d 06h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.