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URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 78

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Rev Log message Author Age Path
78 alu with registered outputs simont 8032d 22h /
77 substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel simont 8041d 19h /
76 add module oc8051_sfr, 256 bytes internal ram simont 8041d 19h /
75 initial import simont 8041d 19h /
74 add module oc8051_wb_iinterface simont 8049d 20h /
73 initial import simont 8049d 20h /
72 fix bug in interface to external data ram simont 8049d 21h /
71 add cache simont 8053d 21h /
70 initial import simont 8053d 21h /
69 add parameters simont 8053d 23h /
68 add instruction cache and DELAY parameters for external ram, rom simont 8053d 23h /
67 add parameters for instruction cache simont 8053d 23h /
66 added xrom_test simont 8054d 19h /
65 add oc8051_icache and oc8051_cache_ram simont 8054d 19h /
64 signal es_int=1'b0 simont 8054d 19h /
63 initial import simont 8054d 19h /
62 fix bugs in instruction interface simont 8054d 19h /
61 fix bug simont 8055d 22h /
60 initial inport simont 8056d 22h /
59 add external rom simont 8060d 17h /

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