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Rev Log message Author Age Path
103 Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) sybreon 6160d 20h /
102 Fix MTS during interrupt vectoring bug (reported by M. Ettus). sybreon 6160d 20h /
101 Made multiplier pause with pipeline sybreon 6170d 17h /
100 multiplier issues sybreon 6170d 17h /
99 Minor cleanup sybreon 6182d 12h /
98 Minor typo sybreon 6182d 14h /
97 Added malloc() test sybreon 6182d 14h /
96 Stalls pipeline on MUL/BSF instructions results in minor speed improvements. sybreon 6185d 14h /
95 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. sybreon 6187d 15h /
94 Prevent fHZD & rBRA[1] sybreon 6189d 13h /
93 Minor enable fix sybreon 6189d 14h /
92 Partitioned simulation model. sybreon 6192d 17h /
91 Made idle thread PC track main PC. sybreon 6193d 23h /
90 Fixed Carry bit bug. sybreon 6193d 23h /
89 Changed simulation kernel. sybreon 6193d 23h /
88 Minor optimisations. sybreon 6194d 15h /
87 Made T0 loop. sybreon 6195d 09h /
86 Some optimisations. sybreon 6195d 09h /
85 Replaced OF/ID blocks with combined block. sybreon 6195d 09h /
84 Added interrupt support. sybreon 6195d 09h /

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