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Rev Log message Author Age Path
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.
sybreon 6337d 03h /
15 Removed ROM file. Please generate it from the SW directory. sybreon 6343d 18h /
14 Added initial interrupt/exception support. sybreon 6343d 18h /
13 Fibonacci rom sybreon 6344d 01h /
12 Minor changes sybreon 6344d 02h /
11 Removed unused signals sybreon 6344d 02h /
10 Fixed minor bugs sybreon 6344d 02h /
9 Extended testbench code sybreon 6344d 02h /
8 Fixed memory read-write data hazard sybreon 6344d 02h /
7 Added CMP instruction sybreon 6344d 02h /
6 Fixed C code bug which passes the test sybreon 6344d 02h /
5 Fixed endian correction issues on data bus. sybreon 6344d 17h /
4 Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by Joon Lee. sybreon 6352d 19h /
3 initial import sybreon 6369d 14h /
2 initial import sybreon 6369d 14h /
1 Standard project directories initialized by cvs2svn. 6369d 14h /

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